Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperaturesKILCHYTSKA, V; COLLAERT, N; JURCZAK, M et al.Solid-state electronics. 2007, Vol 51, Num 9, pp 1185-1193, issn 0038-1101, 9 p.Article

On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS processKILCHYTSKA, V; LEVACQ, D; VANCAILLIE, L et al.Solid-state electronics. 2005, Vol 49, Num 5, pp 708-715, issn 0038-1101, 8 p.Article

On the g_m/I_D-based approaches for threshold voltage extraction in advanced MOSFETs and their application to ultra-thin body SOI MOSFETsRUDENKO, T; MD ARSHAD, M. K; RASKIN, J.-P et al.Solid-state electronics. 2014, Vol 97, pp 52-58, issn 0038-1101, 7 p.Article

Ultra-thin body and thin-BOX SOI CMOS technology analog figures of meritKILCHYTSKA, V; MD ARSHAD, M. K; MAKOVEJEV, S et al.Solid-state electronics. 2012, Vol 70, pp 50-58, issn 0038-1101, 9 p.Conference Paper

3D simulation of triple-gate MOSFETs with different mobility regionsCONDE, J; CERDEIRA, A; PAVANELLO, M et al.Microelectronic engineering. 2011, Vol 88, Num 7, pp 1633-1636, issn 0167-9317, 4 p.Article

Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of meritMD ARSHAD, M. K; KILCHYTSKA, V; EMAM, M et al.Solid-state electronics. 2014, Vol 97, pp 38-44, issn 0038-1101, 7 p.Article

Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxidesRUDENKO, T; KILCHYTSKA, V; FLANDRE, D et al.Solid-state electronics. 2010, Vol 54, Num 2, pp 164-170, issn 0038-1101, 7 p.Article

Influence of HALO implantation on analog performance and comparison between bulk, partially-depleted and fully-depleted MOSFETsVANCAILLIE, L; KILCHYTSKA, V; LEVACQ, D et al.IEEE International SOI conference. 2002, pp 161-162, isbn 0-7803-7439-8, 2 p.Conference Paper

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channelBURIGNAT, S; FLANDRE, D; MD ARSHAD, M. K et al.Solid-state electronics. 2010, Vol 54, Num 2, pp 213-219, issn 0038-1101, 7 p.Article

Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavityKILCHYTSKA, V; CHUNG, T. M; OLBRECHTS, B et al.Solid-state electronics. 2007, Vol 51, Num 9, pp 1238-1244, issn 0038-1101, 7 p.Article

Reduction of gate-to-channel tunneling current in FinFET structuresRUDENKO, T; KILCHYTSKA, V; COLLAERT, N et al.Solid-state electronics. 2007, Vol 51, Num 11-12, pp 1466-1472, issn 0038-1101, 7 p.Conference Paper

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applicationsKILCHYTSKA, V; BOL, D; DE VOS, J et al.Solid-state electronics. 2013, Vol 84, pp 28-37, issn 0038-1101, 10 p.Conference Paper

Characterization and modelling of single event transients in LDMOS-SOI FETsALVARADO, J; KILCHYTSKA, V; BOUFOUSS, E et al.Microelectronics and reliability. 2011, Vol 51, Num 9-11, pp 2004-2009, issn 0026-2714, 6 p.Conference Paper

Effect of high-energy neutrons on MuGFETsKILCHYTSKA, V; ALVARADO, J; COLLAERT, N et al.Solid-state electronics. 2010, Vol 54, Num 2, pp 196-204, issn 0038-1101, 9 p.Article

Investigation of charge control related performances in double-gate SOI MOSFETsKILCHYTSKA, V; CHUNG, T. M; VAN MEER, H et al.Proceedings - Electrochemical Society. 2003, pp 225-230, issn 0161-6374, isbn 1-56677-375-X, 6 p.Conference Paper

Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETsMAKOVEJEV, S; RASKIN, J.-P; ARSHAD, M. K. Md et al.Solid-state electronics. 2012, Vol 71, pp 93-100, issn 0038-1101, 8 p.Conference Paper

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layerRODA NEVE, C; KILCHYTSKA, V; ALVARADO, J et al.Microelectronics and reliability. 2011, Vol 51, Num 2, pp 326-331, issn 0026-2714, 6 p.Article

Silicon-on-Nothing MOSFETs : An efficient solution for parasitic substrate coupling suppression in SOI devicesKILCHYTSKA, V; FLANDRE, D; RASKIN, J.-P et al.Applied surface science. 2008, Vol 254, Num 19, pp 6168-6173, issn 0169-4332, 6 p.Conference Paper

FinFET analogue characterization from DC to 110 GHzLEDERER, D; KILCHYTSKA, V; RUDENKO, T et al.Solid-state electronics. 2005, Vol 49, Num 9, pp 1488-1496, issn 0038-1101, 9 p.Article

Substrate effects on the small-signal characteristics of SOI MOSFETsKILCHYTSKA, V; LEVACQ, D; LEDERER, D et al.ESSCIRC 2002 : European solid-state circuits conferenceEuropean solid-state device research conference. 2002, pp 519-522, isbn 88-900847-8-2, 4 p.Conference Paper

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regimeMD ARSHAD, M. K; MAKOVEJEV, S; OLSEN, S et al.Solid-state electronics. 2013, Vol 90, pp 56-64, issn 0038-1101, 9 p.Conference Paper

High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETsKILCHYTSKA, V; ALVARADO, J; PUT, S et al.Microelectronics and reliability. 2012, Vol 52, Num 1, pp 118-123, issn 0026-2714, 6 p.Article

Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETsKILCHYTSKA, V; ALVARADO, J; COLLAERT, N et al.Solid-state electronics. 2011, Vol 59, Num 1, pp 18-24, issn 0038-1101, 7 p.Conference Paper

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETsALVARADO, J; BOUFOUSS, E; KILCHYTSKA, V et al.Microelectronics and reliability. 2010, Vol 50, Num 9-11, pp 1852-1856, issn 0026-2714, 5 p.Conference Paper

Effective mobility in FinFET structures with HfO₂ and SiON gate dielectrics and TaN gate electrodeRUDENKO, T; COLLAERT, N; DE GENDT, S et al.Microelectronic engineering. 2005, Vol 80, pp 386-389, issn 0167-9317, 4 p.Conference Paper